A 1.03MOPS/W Lattice-based Post-quantum Cryptography Processor for IoT Devices

This work introduces a configurable lattice-based post-quantum cryptography processor designed specifically for lightweight IoT devices. It accelerates the computation of Key-Encapsulation Mechanism (KEM) and Digital Signature Algorithm (DSA) based on module learning with errors algorithm (MLWE). In order to minimize both hardware cost and energy consumption, the processor incorporates a Barrett reduction algorithm method for efficient number-theoretic transform calculations and implements real-time processing for polynomial sampling. The chip is fabricated on a 28 nm CMOS technology process. It achieves the state-of-the-art power efficiencies and latency in MLWE-based PQC.