Ultra-Low Power 60 GHz Class-C Frequency Tripler in 22-nm FDSOI CMOS Technology

This paper presents a 60 GHz class-C frequency tripler, implemented in 22-nm FDSOI (fully depleted silicon-on-insulator) CMOS technology, for ultra-low power and highly integrated radios used in millimeter-wave indoor localization applications. The tripler employs a multi-stage transformer-coupled differential design with band-pass filters to selectively extract and amplify the power at the 3rd harmonic <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(3f₀)</tex> tone while attenuating powers at fundamental <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(f₀)</tex> and second harmonic <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(2f₀)</tex> tones. An integrated bias generator with resistor trimming, improves the tripler robustness to the on-chip process and mismatch variations. The tripler exhibits a maximum conversion gain (CG) and peak conversion efficiency (CE) of -0.7 dB and 12.63%, respectively, at 60 GHz, and a 3-dB bandwidth of 3.6 GHz with a total DC power consumption <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(PDC)</tex> of 7.9mW at 0.8 V supply. A harmonic rejection ratio (HRR) exceeding 45 dB for fundamental and second harmonic tones is achieved. The maximum saturated output power <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(PSAT)</tex> obtained is 0.9 dBm. The circuit occupies 0. <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4 mm²</tex> area, including pads.