Improving GPU Reliability with Software-Managed Pipeline Parity for Error Detection and Correction

Graphics Processing Units (GPUs) are gaining increasing prominence for their high-performance computing capabilities. However, specific critical sectors like avionics expose GPUs to the risk of radiation-induced failures, resulting in component malfunctions and potentially catastrophic consequences. To address this challenge and enhance GPU reliability, fault tolerance techniques become imperative. In this work, we have improved a hybrid fault tolerance approach that leverages software-controlled pipeline parity. Our goal goes beyond merely detecting errors in pipeline registers; we have extended our technique to include error correction. Our protection method allows software engineers to harden assembly-level instructions while offering flexibility in navigating the intricate balance between reliability and cost-effectiveness.