A Gate Driver with a Low-Voltage GaN HEMT for False Turn-on Suppression and Gate Reliability Enhancement of SiC MOSFETs

Gate driver design for fast-switching SiC MOSFETs faces challenges from the gate-loop parasitic inductance, leading to adverse effects such as false turn-on, gate-loop oscillation, and gate overstress. In this work, the false turn-on suppression capability of a single-polarity gate driving scheme for SiC MOSFETs is improved with a low-voltage (LV) GaN HEMT serving as a voltage clamping element for the off-state gate-to-source voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS-off</inf> ). The lateral LV GaN HEMT can switch at a higher speed than the SiC MOSFET, so that the proposed gate driver can eliminate the false turn-on at a user-friendly V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS-off</inf> of 0 V. Thanks to its reverse conduction characteristics, the LV GaN HEMT is also capable of clamping the negative voltage spikes that are shown to be detrimental to the SiC MOSFET's gate reliability. Additionally, the LV GaN HEMT can further accelerate the turn-off process without severe oscillation, and hence reduce the switching loss. GaN and SiC can become mutual beneficiaries in power electronics.