Implementing Power and Signal Dual Modulation (PSDM) should enhance the cost-effectiveness and simplicity of Power Line Communication (PLC) systems. However, up to now this solution was verified for different converters topologies in latency-tolerant applications, which don't require high-speed data communication i.e., few kbps [1] [2], using low Switching Frequencies (SFs) in the kHz range [3] [9] to encode the binary '1' and '0'. Yet, the low transmission bit rate is the major concern for PSDM systems [5]. Enhancing the bit rate is achieved by increasing the SF in PSDM converters [6]; however, a SF of much higher than 1 MHz is required for a bit rate of more than 1 Mbit/s. Although Wide Bandgap (WBG) devices – such as Gallium Nitride (GaN) and Silicon Carbide (SiC) transistors – can afford those High Switching Frequency (HSF), but on the cost of higher switching losses and Electromagnetic Interference (EMI) noise, once opting for classic hard-switching Pulse Width Modulation (PWM) converters. In this paper, the main goal is the enhancement of the PSDM converters' transmission bit rate with a reduced latency in order to be able to transmit the 1 Mbit/s Controller Area Network (CAN) bus as a reference. Therefore, higher SFs in the MHz range will be targeted, to make this solution compatible with high-speed data communication protocols. As well as considering the converters efficiency including switching losses and EMI noise reduction, by adopting soft-switching Quasi-Resonant Converters (QRCs) with Zero-Voltage-Switching (ZVS) topology, which allows for operation at HSFs and at higher input voltages without sacrificing efficiency.
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Allioua et al. (2024) studied this question.
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