Modeling the Effect of Gate-Drain Parasitic Capacitance of a SiC MOSFET in a Half-Bridge During the Soft Turn-Off and Hard Turn-On Transition

A novel frequency-domain approach to quantify the effect of the gate-drain parasitic capacitance of a SiC MOSFET is presented in this paper. The effect of this parasitic capacitance during the soft turn-off and hard turn-on transition of a MOSFET half bridge can cause an undesired spurious turn-on in the soft turned-off switch. The proposed model based on Miller's theorem accurately quantifies the effect and the behavior of the gate loop irrespective of the usage of spurious turn-on mitigating active Miller clamp. The insights drawn in this paper can be used in designing the gate loop of the power MOSFET to avoid undesired spurious turn-on of the MOSFET due to crosstalk. Moreover, the analytical model is validated with hardware experimental results.