The design of voltage mode control (VMC) in a boost converter remains a challenge due to the presence of stable complex conjugate poles and a right-half-plane (RHP) zero, which comes closer to the imaginary axis of the complex 's' plane with increasing load current and/or voltage gain, making it very difficult to design a suitable compensator over a wide load current range. While digital VMC (DVMC) allows real-time controller tuning, existing design methods using a loop-shaping approach make it difficult to meet the desired load transient performance. This paper presents a new algorithm for tuning a digital proportional-integral-derivative (PID) controller by directly shaping the output impedance in a DVMC boost converter, thereby achieving well-damped transient performance, particularly load transient performance over a wide load current range. Analytical design rules using stable pole/zero cancellation and the proposed direct output impedance shaping techniques are presented. A boost converter prototype is developed, and the digital PID controller is implemented using an FPGA device. A comparative study using different design methods is discussed, and superior transient performance using the proposed technique is demonstrated using simulation and experimental results.
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Chatterjee et al. (2024) studied this question.
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