In this work a 1-bit 19T full adder has been designed and proposed, which is fast and highly optimized in terms of power consumption and minimum latency. The proposed circuit have less output capacitance and short-circuit power dissipation which helps in reduction of power consumption. This 1-bit 19T full adder is based on full swing XOR-XNOR and XOR/XNOR gates logic, which offer significant advantages in speed, power consumption, power delay product (PDP), and driving capabilities compared to other full adders now in use. Our designed is based on 45-nm technology and we have simulated it on Cadence virtuoso software. The output results of the simulation confirm that the 1-bit 19T full adder is fast and consumes less power than the existing ones. The unique transistor sizing method is used to optimize the power delay product of the circuit.
No takes yet. Share an insight, caveat, or question.
Singh et al. (2024) studied this question.
Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context: