A Comparative Analysis of Drain Current in Nanoscale MOSFET variants valid for Low Power Digital Applications

Conventional bulk MOSFETs suffer from various short channel effects in the nanoscale regime. An SOI (Silicon-on-Insulator) MOSFET and DG (Double-Gate) MOSFET are the optimized nanoscale device variants of MOSFETs that have emerged in the recent years. Both the devices have inherent advantages of very low junction capacitance, reduced leakage currents and higher drain currents. The proposed work focuses on performing a comparative analysis of currents in a DG MOSFET with that of SOI and bulk MOSFET structures using device modeling approach. The performance of each device in terms of output and transfer currents for different channel length regimes is explored. The modeling of devices is done using an open source 2D/3D TCAD device simulator. The modeling parameters are chosen as per the scale length theory of respective devices. The output results obtained demonstrate the inherent advantages of the proposed DG MOSFET over SOI & bulk variants in the nanoscale channel length regime for low power switching applications