Design of Strong-Arm Latch Comparator for Low Power 12-bit SAR ADC

As wireless communication and the need for low powered circuits is evolving, there is a need for an efficient design for ADCs. One of the crucial components of an ADC is a comparator and its primary purpose is to compare two voltage levels and generate a logical output based on their relationship. Dynamic comparators have a significant advantage of being more power efficient than ordinary comparators. In this paper, Strong-Arm latch comparator circuit is designed. The Strong-Arm latch comparator is designed in 32 nm CMOS technology in the Synopsys tool. This architecture for a comparator is a crucial electronic circuit designed for high speed and precise comparison of two input signals. Its functional components include an input stage that receives signals for comparison, a Strong-Arm stage responsible for swiftly determining the larger input, a latch stage employing positive feedback to capture and maintain the comparison result and an output stage indicating the outcome. The strong-arm phase actively drives one input to hasten the comparison process, enhancing the response time. The Strong-Arm latch has proven to have the least power dissipation. The proposed design has 1.16 μW of power dissipation when V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in_p</inf> >V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in_n</inf> and 1.21 μW of power dissipation when V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in_p</inf> < V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in_n</inf> in the evaluation phase. The proposed design has low power dissipation of 251, and it has a time delay of 0.02.