28.1 A Fully Integrated, Domino-Like-Buffered Analog LDO Achieving –28dB Worst-Case Power-Supply Rejection Across the Frequency Spectrum from 10Hz to 1GHz with 50pF On-Chip Capacitance

In the design of fully integrated low-dropout (LDO) regulators, minimizing the on-chip output capacitance (CL) is of utmost importance, as it predominantly contributes to the silicon area overhead. However, reducing C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> not only compromises the LDO's feedback stability but also adversely impacts its power-supply rejection (PSR). To avoid the stability issues associated with a small C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> , many prior works [1–4] have adopted the internal-pole-dominant (IPD) LDO design, where the dominant pole frequency (ω <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gate</inf> ) is situated at an internal node rather than at the output (VOUT). As depicted on the left of Fig. 28.1.1, IPD LDOs exhibit superior PSR at low frequencies (termed PSRLF) owing to their ample DC-loop gain [1, 2]. However, as the frequency surpasses ω <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gate</inf> , the loop gain's roll-off deteriorates their high-frequency PSR (PSRHF). While supply-ripple-cancellation schemes [3, 4] have been introduced to improve PSR in IPD LDOs, their efficacy might be susceptible to process variations, given that they necessitate accurate and intricate supply-ripple feedforward mechanisms. In contrast to IPD LDOs, output-pole-dominant (OPD) LDOs [5, 6], in which the dominant pole (ωₒᵤₜ) is created at VOUT, favor achieving moderate PSR over a wide frequency range. The high C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> -dominance in OPD LDOs enables the concurrent reduction in both loop gain and output impedance at ω ≥ ωₒᵤₜ, yielding a more uniform PSRLF. Beyond the unity-gain frequency (ωugf), CL functions as a supply-ripple filter, thus guaranteeing an excellent PSR HFHF. However, OPD LDOs demand a higher frequency for the non-dominant pole (ω2 n d) to ensure stability. The top-right of Fig. 28.1.1 shows the insertion of a gate-drive buffer, promoting higher ω2 n d, placed between an error amplifier (EA) and a power PMOS. In this typical design, ω <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</inf> and ω <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> , formed at the buffer input and output, respectively, govern ω2 n d[≈ .(ωB · ωG)0.5 / 2]. Enhancing the buffer's drivability can boost ω <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> due to the reduction in the buffer's output resistance (RB), but it also leads to a decrease in ωB, attributed to the increased input capacitance (CB) of the buffer. This trade-off sets an inherent ceiling on elevating ω2 n d. Consequently, for stability, OPD LDOs still require a considerably large C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</inf> , depressing ωₒᵤₜ(< <ω2 n d), at the expense of silicon real estate.