A 620pF-Compensated Dual-Mode Capacitance Readout IC for Sub-Display TSP with VRR Scan

Capacitive touch screen panels (TSP) have become a prevalent use interaction method over the past decade, owing to their multi-touch capabilities and ease of use. There is a great demand for sub-display panels outside smartphones in emerging form-factor products. When a sub-display is placed on the outer side of a foldable phone, the touch readout system is more susceptible to malfunctions, such as incorrect touch detection with a wet smartphone. Therefore, as shown in Fig. 26.4.1 (top right), both mutual- and self-capacitive sensing are essential for commercial products. Mutual sensing responds to direct contact from a floating conductor such as a water drop (CM. in parallel with a series of CWT 1 and CWT 2), whereas self sensing remains unresponsive. In addition, the variable refresh rate (VRR) update reduces power consumption in display-touch systems. When the update rate shifts from 60Hz to 120Hz via the bridge update frames upon detecting a touch, unexpected display noises are strongly coupled to the touch electrodes, especially in ultra-thin display panels. This paper presents a capacitance readout IC that supports 3.5-to-5-inch sub-display panels. To accommodate variable panel sizes, the transmitter ($T x$) and receiver ($R x$) electrodes can be adjusted to 12/15/18 Tx and 25/22/19 Rx channels, resulting in a total of 37 ~T / Rx channels. Figure 26.4.1 (bottom) shows the overall architecture. To achieve a high SNR, the electrode driving voltage is doubled using an integrated charge pump circuit with a high voltage process (VDDHV) driver. The analog front-end (AFE) can be configured for both mutual- (CM) and self-capacitance (CS) sensing. Moreover, the AFE is divided into the front-AFE, which converts capacitance into a proportional current and compensates for the unresponsive portions of CS, and the back-AFE, which converts that current back into a voltage while removing common-mode noise. Each operates at supply voltages of 3 ~V(VDDMV) and 1.5V (VDDLV), optimizing chip area and reducing power consumption.