15.5 LISA: A 576×4 All-in-One Replica-Spins Continuous-Time Latch-Based Ising Computer Using Massively-Parallel Random-Number Generations and Replica Equalizations

The Ising computer, a hardware accelerator based on the Ising model, has attracted ever-increasing interest as an alternative computer for solving nondeterministic polynomial-time (NP) hard combinatorial optimization problems (COPs) in the real world. Previous digital ASIC solutions [1–3] have demonstrated Ising computing using discrete-time digital processing elements that work as a large spin array while implementing spins using embedded memory with digital arithmetic-logic units for spin operations. While demonstrating low-power Ising accelerations at room temperature, in contrast to quantum annealers based on the superconducting quantum bits (qubits) operating at an extremely low operating temperature (15-20mK) and large power consumption (10100kW) [4], they have fundamental drawbacks for using them in real-world applications. The discrete-time sequential operation makes the Ising operation slow, while bulky digital memory and arithmetic logic circuitry make them difficult to scale up; moreover, they require extra random number generators, which are bulky. Hence, many digital-spin processing elements typically share a few of them, making them difficult to use for solving large-scale problems. In addition, the quality of the Ising computing solutions is relatively low without using extra Hamiltonian lowering techniques, such as simulated and metropolis annealing [1–3]. Recently, mixed-signal Ising accelerators based on a ring oscillator [5] and a latch [6] have been introduced as a compact, high-speed, low-energy alternative to digital implementations. While demonstrating a continuous-time one-shot Ising operation, which enables orders of magnitudes faster operations (e.g., 1000× faster Ising operation for ∼1k spins [6]), many iterations are required to find better solutions. Furthermore, mixed-signal implementations suffer from Hamiltonian degradations due to mismatches between inverters or P/NMOS transistors in their ring oscillator or latch-based spin circuits. In this work, we propose a mixed-signal Ising computer with all-in-one replica latch-based spins, which can find near-ground solutions with massively parallel random number generations and replica equalization techniques (Fig. 15.5.1).