15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia

The ever-increasing demand for energy-efficient computing motivates novel innovations in advanced process technologies. Power through-silicon via (TSV) technology (PowerVia) [1], [2] is introduced to utilize low-resistance interconnects on the backside as a power-delivery network (PDN); its benefits include a reduced IR drop in the PDN and relaxed signal-routing congestion on the frontside. By using a technology with PowerVias, a fabricated CPU core achieved >90% standard-cell placement density and demonstrated ~6% higher performance, with ~30% lower IR drop [2]. Incorporation of PowerVias in SRAM array design carries unique tradeoffs, compared to logic design, which require a careful bitcell and array peripheral circuit design to enable an energy-efficient and a dense embedded memory. This paper presents a 108Mb high-current 6T-SRAM (HCC) and a 124Mb high-density 6T-SRAM (HDC) design implemented in Intel 4 with PowerVia technology, demonstrating improved or comparable V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</inf> and improved performance with 2% higher bit density for the 2048×60m4 HCC instance compared to similar array designs not using PowerVia [3]. In addition, high-volume manufacturing Si data confirms that there is no unique yield or performance failure mode due to PowerVia.