A Low Voltage 6T SRAM Cell Design and Analysis Using Cadence 90nm And 45nm CMOS Technology

This research investigates the performance optimization of a 6T SRAM cell design in 90nm and 45nm technologies. Focused on reducing both power consumption, access time and area the study utilizes Cadence tools for transient and DC analysis, employing the GPDK for 90nm and 45nm technologies. The proposed CMOS-based 6T SRAM cell design demonstrates notable improvements in power efficiency, area and read/write delay compared to existing 180nm and 45nm technologies. Simulation results in Cadence Virtuoso validate the effectiveness of the enhanced design, showcasing its applicability in modern VLSI applications. This work contributes to advancing semiconductor technology by presenting a refined 6T SRAM cell design tailored for 90nm and 45nm technologies. The outcomes underscore the potential for superior performance in memory design, aligning with the pursuit of energy-efficient and high-speed VLSI applications.