This paper presents Gated Vdd and MTCMOS techniques to achieve low power from the simulated static random-access memory (SRAM) cells. These techniques are implemented on 4 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</tex> , 5 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</tex> and 6 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</tex> memory circuits based on CMOS logic. A significant research work is already in progress in the field of electronics embedded with memory with low power technology for system on chip ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</tex> oC). One of the most popular memory cells is 6 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</tex> SRAM for microprocessor and micro controller architectures for low power applications. This research paper discusses CMOS based SRAM circuits and the parameters considered are power dissipation and delay. Along with 6 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</tex> , the other two memory cells (4 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</tex> and 5 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</tex> ) are also simulated with modifications of the low power techniques. Delay and power dissipation are analyzed for the conventional designs and modified designs with low power methodology. Low power techniques like Gated Vdd and MTCMOS (Multi Threshold CMOS), have been instrumental in reducing the power consumption at 45nm node technology. All the designs are simulated and compared to ponder on best outcome. Comparative analysis shows that the MTCMOS based SRAM cells (specially 6 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</tex> ) represent overall a better choice for reduced power dissipation and delay.
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Dhariwal et al. (2024) studied this question.
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