Memristor-Based Power Efficient 4T3M SRAM Cell

Cells for Random Access Memory (RAM) are extensively utilized in many modern electronic devices. One of the difficult aspects of building Static Random Access Memory (SRAM) cells is power consumption, particularly for ultra-low power applications like implanted biomedical devices. reducing the supply voltage is a frequent method of lowering power consumption in Complementary Metal Oxide Semiconductor (CMOS) SRAM cells. Yet this indicates a reduction in process technology, which has an impact on read and write stability. Therefore, a novel SRAM design that makes use of memristors has been presented in this work in order to address this difficulty. In addition to offering improved stability, this architecture uses less power. In this paper, analysis of Static Noise Margin (SNM), delay and power consumption have been performed for the novel design using 65nm technology in Cadence Virtuoso. To the best of author's knowledge, no prior proposals for this SRAM design have been made. After comparing the values with several memristor-based designs, the proposed 4T3M design showed approximately 3 times less power consumption than other memristor-based memories.