CNTFET Based Low Power SRAM Design: Architectures, Challenges and Innovative Implementations

Static Random Access Memory (SRAM) takes on a vital role in digital technology especially for applications that demand high speed and low power consumption. However, there are top priority with leakage power, reliability and stability owing to continuous technological advancement and the demand for energy efficient systems. Thorough research of low power SRAM design approaches is presented with an emphasis on cutting edge cell topologies and innovative device technologies. Power efficiency, read/write stability and area overhead are examined for various SRAM designs including 6T, 7T, 8T, 9T and 10T cells. Special attention is focused on SRAM designs using Carbon Nanotube Field Effect Transistor (CNTFET) which provide excellent electrical characteristics and less leakage than conventional silicon enabled methods. Subthreshold operation and assist methods that enable ultra low voltage capability are also included in the article. To further emphasize the need of low power SRAM designs, growing application domains like Internet of Things (IoT), biomedical systems and Compute-In-Memory architectures are investigated. Major performance deals and design trends are identified through a comparative analysis of this research. In order to facilitate growth of next generation low power SRAM systems, important challenges and future research directions are finally specified.