Atomic-Layer-Deposited Ultrathin InAlZnO FETs-Based 2T0C DRAM Cells With Long Data Retention and Multilevel Storage

Ultrathin InAlZnO (IAZO) channel thin-film transistors are fabricated using plasma-enhanced (PE) atomic layer deposition (ALD) under a maximum process temperature of 200 °C. By optimizing the Al doping content, the proposed IAZO transistor exhibits a near-zero threshold voltage ( <tex-math notation="LaTeX">Vₜₕ) </tex-math> , a quite small subthreshold swing (SS) of 75 mV/dec, and an OFF-state leakage current ( <tex-math notation="LaTeX">Ioff) </tex-math> below the detection limit ( <tex-math notation="LaTeX">10^-18 </tex-math> A/ <tex-math notation="LaTeX">μ m </tex-math> ) at temperatures up to 125 °C. The gate bias stress stabilities of the IAZO transistor are significantly improved by using an ALD Al2O3 passivation layer on the back surface of channel, that is, the <tex-math notation="LaTeX">Vₜₕ </tex-math> shifts are reduced to 0.03 and −0.08 V after 60 min stress at 3 and −3 V, respectively. Moreover, the <tex-math notation="LaTeX">Vₜₕ </tex-math> and <tex-math notation="LaTeX">μ FE </tex-math> only change by ~2.3% and ~6.9% after experiencing post-annealing at 400 °C for 60 min in N2, indicating an extraordinary thermal stability. Finally, the IAZO transistors-based 2T0C DRAM cells are fabricated, demonstrating a fast write speed of 100 ns, a long retention time of >30 ks, and a 2-bit multilevel storage characteristic. These results illustrate that the ALD IAZO transistor is a promising candidate for the back-end-of-line (BEOL) compatible DRAM applications.