A Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2-D/3-D Partial Differential Equations

This work presents a digital hardware accelerator with compute-near-memory to solve 2-D and 3-D partial differential equations (PDEs) using the finite difference method (FDM). The proposed hardware accelerator is reconfigured to solve 2-D/3-D Laplace and Poisson equations, and it scales to solve larger 2-D problems with no additional overhead. The reconfigurable and scalable architecture is implemented by building a 16 <tex-math notation="LaTeX">×</tex-math> 16 near-memory bit-serial processing element (PE) array and four 16 <tex-math notation="LaTeX">×</tex-math> boundary PEs with 92-kb static random-access memory (SRAM) distributed in the PE array. The proposed near-memory bit-serial computing architecture reduces data movement and achieves higher energy efficiency than the conventional Von Neumann architecture. The bit-serial computing architecture allows the PEs to communicate with neighbors via a minimal communication bandwidth (1 bit). The proposed hardware accelerator finds numerical solutions to 2-D PDEs (with up to a 64 <tex-math notation="LaTeX">×</tex-math> 64 grid size) and 3-D PDEs (with up to a 16 <tex-math notation="LaTeX">×</tex-math> 16 <tex-math notation="LaTeX">×</tex-math> 16 grid size) using FDM. A prototype chip is fabricated using 65 nm, occupying a 1.78-mm <tex-math notation="LaTeX">^2</tex-math> die area. The measured energy to solve the 2-D/3-D PDE for updating an entire grid is 0.7 nJ/1.14 nJ at 1 V and 25.6 MHz.