Hardware implementation of AV1 fraction motion estimation

A 4-tap coefficient, 8-neighborhood subpixel search algorithm is presented in this paper to simplify hardware implementation. This algorithm is intended to be used for the fraction motion estimation module of the AV1 video coding standard. A 32 × 32 block is used as the fundamental unit for searching and interpolation in hardware implementation. Blocks of the same MV are combined in a merge grouping method to perform subpixel searches, improving search efficiency. The search method for the eight subpixel points of the current MV in a clockwise order is used to realize continuous reading data without stopping the flow, improving the work efficiency of the pipeline. Finally, a shift-and-add method is employed to implement the multiplication calculation of fixed coefficients, fully utilizing the common factor between the coefficients to reuse part of the circuit and other approaches to effectively reduce the expenditure of hardware. The interpolation and searching process of subpixels is implemented in Verilog HDL, and synthesis is performed using Design Compiler under 55 nm process conditions at SMIC with an operating frequency of up to 200 MHz, an area of 5894809.13 µm2, and a power consumption of 352.21 mW.