A multi-objective optimization register clustering method

The clock tree synthesis (CTS) step is critical for the physical design of ultra-large-scale integrated circuits (VLSI). Outstanding CTS results can reduce the skew of clock networks, decrease chip power consumption while improving performance and reliability of the chip. This paper proposes a register clustering method based on the nondominated sorting genetic algorithm II (NSGA-II) algorithm to generate the leaf-level topology of the clock tree, addressing multi-objective optimization issues in integrated circuit physical design. We model register clustering as a multi-objective optimization problem. By analyzing the clock network model and power consumption to design the objective functions, register clustering schemes are encoded. Pareto optimal solutions are obtained through iterative evolution and non-dominated sorting. This method is integrated into the traditional CTS process. Three circuits were selected from the ISCAS89 benchmark circuit for testing and analysis proving its effectiveness. Experimental results show that compared to traditional clock tree synthesis methods, our approach reduces timing skew by more than 5%, maximum clock delay by over 15%, and power consumption by over 10%. Our strategy achieves a balance among multiple physical design objectives, obtaining superior clustering schemes. This paper offers an effective algorithm for multi-objective register clustering.