A Low-Noise Dual-Path Self-Interference Cancellation Architecture for Watt-Level TX Power Handling in Simultaneous Transmit and Receive

Mitigating self-interference (SI) is vital for advancing simultaneous transmit and receive (STAR) systems. The noise and linearity of the canceller impose limitations on SI power handling. This article proposes a novel dual-path SI cancelling scheme for high-power SI handling. The proposed approach breaks self-interference cancellation (SIC) tradeoffs between operating frequency, SI power handling, and canceller noise/distortion by using a frequency-translated (FT) SI canceller and an auxiliary FT noise-cancelling (NC) path that cancels the noise/distortion from the primary canceller. This approach can work well for both full-duplex (FD) and frequency-division duplex (FDD) schemes. The 65-nm CMOS implementation achieves <tex-math notation="LaTeX">~</tex-math> 45-dB SIC for 12-dBm receiver (RX) SI peak power (9-dBm avg.) with only 4-dB noise figure (NF) degradation and 207-mW power consumption at 600 MHz. The SIC approach enables a blocker-1 dB with respect to SI of <tex-math notation="LaTeX">$>$</tex-math> 16 dBm (8 <tex-math notation="LaTeX">×</tex-math> higher than prior work) while operating from 0.5 to 1.3 GHz. Therefore, this implementation can support watt-level SI power handling with transmitter (TX)–RX isolation <tex-math notation="LaTeX">$>$</tex-math> 15 dB. This is demonstrated through measurements that show 30-dBm TX power handling with 22-dB initial isolation from the circulator.