Efficient mmWave PA in 90nm CMOS: Stacked-Inverter Topology, L/T Matching, and EM-Validated Results

In this study, we present the design and analysis of a stacked inverter-based 1 millimeter-wave (mmWave) power amplifier (PA) in 90nm CMOS targeting wideband Q-band operation. The PA employs two PMOS and two NMOS devices in a fully stacked inverter topology to distribute device stress, remove the need for an RF choke, and increase effective transconductance while preserving compact layout. A resistor ladder biases thestack near VDD/4 per device, and capacitive division steers intermediate-node swings to enable class-E-like voltage shaping at the output. Closed-form models are developed for gain, output power, drain efficiency/PAE, and linearity, alongside a small-signal stacked-ladder formulation that quantifies stress sharing and the impedance presented to the matching networks; L/T network synthesis relations are provided to co-optimize bandwidth and insertion loss. Post-layout simulation in 90nm CMOS shows |S21| = 10 dB at 39.84GHz with 3 dB bandwidth from 36.8–42.4 GHz, peak PAE of 18.38% near 41 GHz, and saturated output power Psat = 8.67dBm at VDD = 4V, with S11 < −15 dB and reverse isolation ≈ −16 dB. The layout occupies 1.6×1.6mm2 and draws 31.08mW. Robustness is validated via a 200-run Monte Carlo showing tight clustering of Psat and PAE, sensitivity sweeps identifying sizing/tolerance trade-offs (±10% devices/passives), and EM co-simulation of on-chip passives indicating only minor loss/shift relative to schematic while preserving the target bandwidth and efficiency. The results demonstrate a balanced gain–efficiency–power trade-off with layout-aware resilience, positioning stacked-inverter CMOS PAs as a power and area-efficient solution for mmWave front-ends.