Comprehensive Analysis of Tree-shaped Nanosheet FETs in Junctionless, Accumulation, and Inversion Structures at Sub-5 nm Node for Next-Generation Digital, Analog/RF and Circuit Applications

This work for the first time presents a comprehensive evaluation of TreeFET device operating in accumulation (ACC), junctionless (JL), and inversion (INV) structures for digital, analog/RF, and circuit applications at the sub-5 nm node. Initial comparisons among the three structures reveal that JL-based TreeFET exhibit superior analog/RF performance at the cost of reduced cutoff frequency (fT), while INV TreeFETs demonstrate optimal digital performance with a compromise in subthreshold swing (SS). Temperature-dependent performance analysis, conducted across a range of 250 K to 375 K, demonstrates that reduced temperatures significantly improve the digital, analog/RF characteristics for all three operational structures. Further analysis involving gate length (Lg) variations from 12 nm to 18 nm highlights that reduced Lg is advantageous for RF applications but not recommended for digital and analog performance improvements due to degradation in key parameters. The CMOS inverter designed with the JL TreeFET exhibits the lowest delay (~3.51ps) due to reduced parasitic capacitances, making it suitable for high-speed digital circuits. Furthermore, the CMOS inverter gain is marginally higher in the INV structure (~9.86) compared to the JL and accumulation structures, with only a ~5% improvement over the JL structure. These findings provide critical insights into the trade-offs and application-detailed optimization of TreeFETs in structure-specific operation.