A 1.5-GS/s Clock Gating Flash ADC with 32.63-dB SFDR and 4.59-Bit ENOB in 0.18µm CMOS

Abstract ADCs transform analog sensor readings into digital data that Microcontrollers and Processors may use in control algorithms for the majority of applications, such as Robotics, Industrial Instrumentation, Automation and Internet of Things (IOT) devices. Several methods were suggested to convert the analog signal to a discrete signal the analog signal's inaccuracy prevented a successful conversion. High resolution Flash ADC is constructed using MOSFET devices in reliable VLSI circuits to reduce power dissipation. A Novel 1.5 GS/s Clock Gating (CG) Flash ADC was proposed in this study and it involves a low switching power Clock Gating NOR-LTE comparator used to avoid the occurrence of race condition by minimizing the clock skew and jitter, an Adaptive Priority Encoder and Inverted AND Gate Bubble Error Controller. Execution of the suggested CG Flash ADC takes place on a 0.18µm Tanner EDA tool with 0.8V power supply. The observed minimum and maximum power consumption is 10.63mW and 15.45mW at -20°C and + 60°C respectively that is equal to 30% variations compared to the conventional method. The measured values of SNDR and SFDR of the proposed 5-bit 1.5GS/s CG-FADC are 29.45 dB and 32.63 dB, with a resulting ENOB of 4.59 bits.