A Low‐Power, Highly Tunable Ring Oscillator Architecture Based on a QFGT‐Modified Maneatis Cell

The proposed work introduces a low‐power ring oscillator architecture that achieves enhanced tunability by incorporating quasi‐floating gate transistors (QFGTs) into a modified Maneatis delay cell. The proposed CMOS design features a local feedback mechanism at the load node, which establishes a summing point at the complemented output through the QFGTs configuration. The capacitive divider ratio associated with the QFGT structure defines a programmable feedback factor (), allowing flexible control of the phase delay and consequently of the oscillation frequency. The proposed circuit is mathematically modeled and validated through simulations using a TSMC 180 nm CMOS process. Evaluations are performed through 500‐run Monte Carlo simulations and analyses of process corner variations to assess robustness.