Abstract Error correction coding has been integral to digital communications since the introduction of Hamming codes andReed-Solomon codes, with Low-Density Parity-Check (LDPC) codes later enhancing performance in modern systems. This workpresents a hardware-based implementation of a resilient and efficient wireless communication system that integrates LDPCand Reed-Solomon (RS) codes for robust error correction. The architecture employs an LDPC (8,7) code as the outer code andan RS (8,2) code as the inner code, with interleaving applied between them to effectively mitigate burst errors and inter symbolinterference (ISI). The RS decoder is implemented using the Modified Euclidean Algorithm (MEA), enabling efficientsymbol-level error correction with reduced hardware complexity. The entire design is modeled in VHDL and synthesized using theXilinx Vivado Design Suite for deployment on a Zynq-7000-based ZedBoard FPGA. Wireless transmission is carried out via theHC-12 SI4463 transceiver operating at 433MHz. Simulation and on-board testing demonstrate that the concatenated LDPC–RScoding approach significantly improves bit error rate (BER) performance under noisy and dispersive channel conditions.The proposed system offers a reliable and resource-optimized solution for embedded wireless applications and FPGA-basedcommunication platforms.
Verma et al. (Wed,) studied this question.