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October 18, 2025Open Access

Hardware-Described Nanoscale Carry-Save Adder in Quantum-Dot Cellular Automata: An Optimised Design and Evaluation Framework

Key Points

The proposed QCA-based architecture achieves a 34.29% reduction in total cells compared to previous designs.
Using only 46 QCA cells, the architecture improves delay and minimizes energy consumption significantly.
Modeling with Verilog ensures functional equivalence, reinforcing the hardware relevance of nanoscale QCA circuits.
Simulation results confirm the design's correctness and stability, suggesting QCA as a viable alternative to CMOS technology.

Abstract

Quantum-dot Cellular Automata (QCA) technology has emerged as a promising approach for constructing nanoscale digital circuits, offering notable advantages such as minimal power consumption, rapid processing speeds, and highly compact layouts. Traditional CMOS technology faces significant challenges at the nanoscale, including reduced gate control and increased current leakage. QCA, on the other hand, provides a robust platform for building next-generation digital systems. In this study, a unique single-layer QCA-based Full-Adder (QCAFA) and Carry-Save Adder (CSA) architecture is developed to enhance key performance factors such as delay, space, cost, and cell block count. The outlined designs demonstrate superior efficiency compared to state-of-the-art single-layer and multilayer QCA designs. Simulation results conducted with QCADesigner 2.0.3 and QCADesigner-E reveal that the proposed architecture achieves a substantial 34.29% diminution in total cells compared with the recent design, utilising only 46 QCA cells. Similarly, for the CSA, the proposed design attains an 18.62% reduction in cell count compared with its best counterpart, utilising only 424 QCA cell blocks. To enhance design credibility and hardware relevance, this research additionally models and validates the architecture using the Verilog hardware description language (HDL Version 12.0), thereby bridging the gap between nano-architecture and HDL-based prototyping. Simulation results obtained through QCADesigner confirm the correctness and stability of the QCA layout, while HDL simulation verifies functional equivalence at the behavioural and structural levels. The proposed designs not only enhance speed and reduce energy consumption but also offer better manufacturability. The findings of this study highlight the potential of QCA technology as a feasible substitute for CMOS for high-performance digital arithmetic circuits at the nanoscale.

Hardware-Described Nanoscale Carry-Save Adder in Quantum-Dot Cellular Automata: An Optimised Design and Evaluation Framework

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