Titan-I: An Open-Source, High Performance RISC-V Vector Core

Vector processing has evolved from early systems like the CDC STAR-100 and Cray-1 to modern ISAs like ARM's Scalable Vector Extension (SVE) and RISC-V Vector (RVV) extensions. However, scaling vector processing for contemporary workloads presents challenges due to overheads in traditional architectures. We introduce Titan-I (T1), an out-of-order (OoO) RVV architecture designed to scale both Instruction-Level Parallelism (ILP) and Data-Level Parallelism (DLP). T1 incorporates a coarse-grained floor-planning solver, a datapath-wide permutation unit, and a register cache for mask registers, improving bandwidth and reducing latency. It also uses multiple OoO techniques, such as fine-grained chaining, issue-as-commit and memory interleaving, to optimize ILP for wider vector datapaths. T1 outperforms General Purpose Graphic Processing Units (GP-GPU) and other vector cores, achieving up to 1.85 × speedup over GB202 (Nvidia 5090) and up to 2.41 × speedup over GA102 (Nvidia 3090) in cryptography with 40% of SM's area of GA102. In HPC workloads, T1 offers a compatible performance with 19% area of HiSilicon TaiShan V120 (KP920), achieving a 4.59 × speedup over it when scaling T1's datapath 4 ×. T1 also exhibits robust tolerance to memory latency, achieving an 8.05 × performance improvement over the SpacemiT X60 (K1) in pure DDR mode.