Analysis reveals interfacial thermal resistance in silicon carbide interfaces, suggesting improvements for power module packaging.
The driver control chips for high-power silicon carbide (SiC) power devices rely on silicon-based CMOS processes, which lead to parasitic effects and thermal management bottlenecks. Customisable design of nanotransition layers for SiC surface-activated bonding (SAB) has demonstrated significant application value. However, current SAB research focuses on process validation of specific material combinations and lacks understanding of the underlying principles governing surface-activated bond design. The experimental findings suggest that the sputtering-deposition time, rather than the Ar atom bombardment time, plays a pivotal role in the control of the bonding interface. In the initial stage of sputtering-deposition, the deposited layer exhibits a low density, leading to a thicker and inferior interface. As time increased, the deposited layer undergoes a gradual densification process, ultimately resulting in the formation of Fe single-crystal interfaces and the establishment of atomic-level bonding between Fe and SiC. Molecular dynamics simulations confirm the fracture mechanism at the single-crystal SiC/Fe/SiC interface, where fracture occurs within the Fe transition layer. In addition, the interfacial thermal resistance of SiC/Fe/SiC interface (4.53 m2K/GW) is lower than that of the thinner amorphous carbon SiC/a-C/SiC interface (6.74 m2K/GW). The present work reveals a universal theoretical framework for expanding the application of surface activation bonding technology in power module packaging, photonic integration, and other fields.
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Zhao et al. (2025) studied this question.
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