FPGA-Deployable PCNN-Based Neural Network Implementation for Real-Time Speech Recognition

This paper describes a neural network algorithm-based FPGA-implemented real-time human speech denoising approach. In the realm of speech processing, neural networks have become increasingly popular as artificial intelligence technology advances. Applying real-time voice denoising to embedded systems with limited resources remains challenging. In addition to denoising, this work explores feature extraction for speech recognition, with particular attention to spectrogram-based methods using a pulse-coupled neural network (PCNN). We suggest a neural network-based technique to address this issue, and we put it into practice using FPGAs to handle human speech noise in real time. We refined a neural network architecture for human speech inputs and developed it for FPGA hardware acceleration. The experimental findings demonstrate the tremendous advancements our method makes in real-time and denoising effect, while also showing the potential of PCNN features to improve recognition stability and offer a fresh perspective on how to effectively apply speech processing in embedded systems. The overall improvement of the system was an average of [Formula: see text] [Formula: see text]dB in SNR, and when evaluated in noisy conditions, an additional [Formula: see text] PESQ and [Formula: see text] STOI could be gained. This implementation (on a Xilinx Zynq-7020 FPGA) consumed approximately 21% for LUTs, 18% for DSPs, and 25% for BRAM. It had a latency of 1.8[Formula: see text]ms and 1.2[Formula: see text]W power consumption. The FPGA design turned out to be [Formula: see text] faster than the CPU in standard configurations, which saves over 70% of energy, making it possible to implement real-time speech denoising.