A 5.3 to 6.2-GHz Fractional-N Frequency Synthesizer with Variable Gain Automatic Frequency Calibration Using Cycle Slips in 65 nm CMOS

The paper presents an automatic frequency calibration (AFC) technique for a charge pump-based phase-locked loop (CPPLL) with 5–6 μsec correction time. The architecture detects frequency offset in real time while keeping the loop active and performs a variable gain calibration that increases the correction gain at large frequency offsets to accelerate lock acquisition and gradually reduce the gain near locking frequency to suppress residual oscillation and overshoot. The implemented synthesizer rapidly re-acquires the lock within several adjacent coarse-tuning codes after frequency drift and maintains continuous operation without interruption. It demonstrates that the designed AFC achieves seamless frequency recovery in dynamically varying environments. Fabricated in a 65 nm CMOS process, the prototype fractional-N synthesizer occupies an active area of 0.603 mm2 and operates over a 5.3–6.2 GHz tuning range. At 5.8 GHz, the design achieves a phase noise of −107 dBc/Hz at 1 MHz offset and consumes 21.5 mW from a 1.2 V supply.