Multicycle tests improve fault coverage in benchmark circuits, suggesting benefits of test data compression and functional clock synchronization.
Test data compression supports reductions in test data volume and test application time. The use of multicycle scan-based tests with several functional capture cycles between scan operations supports test compaction beyond that possible with single-cycle or two-cycle tests. Multicycle tests with constant primary input sequences are used for avoiding the need to synchronize the primary input sequence with the functional clock. However, this prevents the detection of delay faults in the output cone of the primary inputs. A different solution is to produce the primary input sequence of a multicycle test by the on-chip decompression logic in addition to the scan-in state. This approach is considered in this article. The key new contribution of the article is to extend the scan chain that drives the primary inputs, and add design-for-testability ( DFT ) logic, to ensure that the primary input sequences produced by the decompression logic are suitable for the application of multicycle tests. Experimental results for transition faults in benchmark circuits demonstrate significant fault coverage improvements and significant test compaction.
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Irith Pomeranz (2025) studied this question.
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