Abstract Today, the latest impressive evolution and adaptation has been achieved by VLSI technology and advancement for smart industries is also going on this field. To reach these platforms, this credit goes to scaling down the aspect ratio. The measurements of the MOSFETs have not been reduced, but also the rebellion is moving all circuits from MOSFET to one new emerging device. This paper highlights the analysis of the new issue of reliability, i.e., noise voltage which affecting the SRAM cell retention voltage. For comparison with the effect of aspect ratio using Cadence Virtuoso tool, simulation results are taken on the Memristor based 8T SRAM cell and the conventional 8T SRAM cell with 45 nm technology. This article is protected by copyright. All rights reserved.
Mishra et al. (Fri,) studied this question.