OpenFPGA-NoC: Automated Fabric and Bitstream Generation for NoC-based FPGAs

As the demand for high-performance and flexible hardware accelerators increases, Network-on-Chip (NoC)-based Field Programmable Gate Arrays (FPGAs) offer a scalable solution for complex, data-intensive applications. While commercial FPGA vendors like Xilinx, Altera, and Achronix offer hardened NoCs in their flagship architectures, there are no academic or open-source FPGAs with embedded NoCs. Although many open-source soft NoC implementations exist, they pose challenges like high resource utilization and low frequencies, making them unsuitable for high-performance applications. Vendor-supplied FPGAs with fixed hard NoC topologies may not satisfy the requirements of new application domains, motivating the need to enable automatic design of customized NoC-based FPGAs. To address this need, we introduce OpenFPGA-NoC, an automated flow that generates fabric netlists and bitstreams for NoC-based FPGAs. Our work extends the OpenFPGA framework by adding a NoC-specific tag in the OpenFPGA architecture description, supporting custom configuration ports to handle address mapping of NoC routers, automating the generation of architecture files, and enabling a custom RTL-to-bitstream flow. OpenFPGA-NoC provides an easy-to-use interface that allows the FPGA architect to exploit the flexibility provided by the framework- providing NoC parameters like topology, number of routers, and key router parameters like data widths and buffer depths. By providing push-button flows, OpenFPGA-NoC significantly lowers the barrier to designing high-performance FPGA fabrics.