125‐GHz‐band RF receiver front end using 40 nm complementary metal–oxide–semiconductor technology

This paper presents a 125‐GHz‐band radio‐frequency (RF) receiver front end designed for radar applications using 40 nm complementary metal–oxide–semiconductor (CMOS) technology. The receiver front‐end chip integrates a five‐stage single‐to‐differential low‐noise amplifier, transconductance I/Q driver, quadrature I/Q passive mixer, quadrature I/Q transimpedance amplifier, single‐to‐differential local oscillator (LO) driver, and quadrature I/Q LO generator. Designing an I/Q receiver front end for the 125‐GHz band is particularly challenging due to the difficulty of generating and maintaining well‐matched I/Q signals at such high frequencies. This work demonstrates highly matched I/Q signal outputs using a simplified circuit architecture that achieves both low power consumption and a compact core chip size. Measurement results of the RF receiver front‐end chip reveal a conversion gain of 30 dB, 3 dB bandwidth ranging from 121 GHz to 129 GHz, an input P1dB of −30 dBm, and a double‐sideband noise figure of 11.4 dB. The measured gain and phase mismatches between the I and Q channels are only 0.1 dB and 3.6°, respectively. The chip operates with low power consumption, drawing only 80 mA from a 1 V supply. It also features a compact core area of 0.22 mm 2 .