Key result
Design 3 of the AFib ECG detection module cuts resource utilization to 1 logic unit.
A high-level synthesis approach successfully mapped the natural frequency algorithm of ECG signals into an RTL design for atrial fibrillation detection, with a single-cycle design (Design 2) offering the optimal balance of logic utilization and execution time.
Low-resource ECG designs advance hardware feasibility for AF detection; leaves open clinical validation and real-world performance.
The growth of interest in the development of reduced-scale electrocardiogram (ECG) system based on field-programmable gated-array (FPGA) design platform is increasing. This study provides initial result of mapping digital signal processing to hardware design for specific purpose. In this paper, a part of digital signal processing for atrial fibrillation classification was implemented to register-transfer level (RTL) design. The specific part was feature extraction of ECG signal. The algorithm of ECG signal feature extraction was natural frequency from second-order system for detecting atrial fibrillation. By applying high-level synthesis method, three designs were implemented for natural frequency behavior. The designs were two Single-Cycle (Design 1 and Design 2) and Multi-Cycle fully-constraint (Design 3), of which logic utilization consist of 2530, 36 and 1, respectively. Performance evaluation among all designs were compared.
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Abdul-Kadir et al. (2015) studied Atrial Fibrillation. Natural Frequency of ECG Signal Detection Module was evaluated on Natural frequency of ECG signal detection. Natural Frequency of ECG Signal Detection Module effectively utilized only 1 logic unit in Design 3, significantly reducing resource utilization compared to Designs 1 (2530 units) and 2 (36 units).
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