Impact of dielectrics on the electronic properties of ultrasmall nanoscale silicon

For decades the number of transistors per area has been halved approximately every two years, increasing the computational power of integrated circuits, while the transistor size approached few nanometers and slowed down significantly. The reduction in feature size is limited by two factors. The first is related to the distribution and deactivation of dopant atoms in small devices, used to establish good electrical contacts into the devices, and the second is related to quantum mechanical broadening of the band gap in devices on the length scale of approximately 5nm and smaller due to quantum confinement. DFT calculations of intrinsic Si nanocrystals embedded in different dielectrics predicted an Nanoscale Electronic Structure Shift Induced by Anions at Surfaces (NESSIAS) in the band structures of the nanocrystals and a smaller influence of the quantum confinement. Embedding Si nanocrystals in SiO2 was predicted to shift the band edges of the valence and conduction band below those of bulk-Si and in case of Si3N4 above them. From DFT calculations of nanowire with abrupt changes of the embedding dielectric sharp transitions of the band edges on the order of 1 nm are expected. The scope of this thesis was the improvement and development of fabrication processes for Si nanowells embedded in SiO2 and Si3N4 for the determination of the valence and conduction band edge as function of the nanowell thickness and dielectric by ultraviolet photoelectron spectroscopy and X-ray absorption spectroscopy and for electrical characterization. Major contributions have been made by demonstrating good process control on fabricating Si nanowells in SiO2 involving thinning down the top-Si of silicon on insulator and Si nanowells in Si3N4 involving thinning down the top-Si, rapid thermal nitridation, wafer bonding and wafer etching. The band gaps obtained from measurements on these samples confirmed that quantum confinement is counteracted by NESSIAS in Si nanowells between 1.5nm and 4.0nm. Samples comprised of Si nanowells in SiO2 have been fabricated for electrical characterization by transport measurements and a fabrication process for the characterization of Si nanowells embedded in Si3N4 was proposed.