What question did this study set out to answer?

The aim is to implement a resource-efficient and low-power version of the Q-learning algorithm on FPGAs.

January 18, 2026PeerJ Computer ScienceOpen Access

Resource-efficient and low-power implementation of the Q-learning algorithm on FPGA

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This article demonstrates a low-power Q-learning algorithm in FPGA, highlighting significant resource efficiency improvements.

The aim is to implement a resource-efficient and low-power version of the Q-learning algorithm on FPGAs.
Implemented Q-learning algorithm on Genesys 2 Kintex7 FPGA.
Utilized temporary memory to optimize Q-value updates.
Analyzed design across various state scenarios and fixed-point formats.
Achieved 71.9% reduction in LUTs with 1,024 states at 16 bits.
Achieved 66.4% reduction in FFs and 75.6% reduction in BRAMs at the same configuration.
Achieved 67% reduction in power consumption with 1,024 states at 16 bits.
Maintained performance with a convergence to optimal policy.

Bazmalah et al. (2026) studied this question.

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January 18, 2026PeerJ Computer ScienceOpen Access

View Full Paper

Ask AI

Bookmark

Authors

This article demonstrates a low-power Q-learning algorithm in FPGA, highlighting significant resource efficiency improvements.

The aim is to implement a resource-efficient and low-power version of the Q-learning algorithm on FPGAs.
Implemented Q-learning algorithm on Genesys 2 Kintex7 FPGA.
Utilized temporary memory to optimize Q-value updates.
Analyzed design across various state scenarios and fixed-point formats.
Achieved 71.9% reduction in LUTs with 1,024 states at 16 bits.
Achieved 66.4% reduction in FFs and 75.6% reduction in BRAMs at the same configuration.
Achieved 67% reduction in power consumption with 1,024 states at 16 bits.
Maintained performance with a convergence to optimal policy.

Bazmalah et al. (2026) studied this question.

View Full Paper

Ask AI

Bookmark