CADAS: Communication-Aware Dynamic Scheduler on CGRAs for Large-Volume and Real-Time Processing

Modern data-intensive applications demand accelerators that can adapt to dynamic and high-throughput workloads. Coarse-Grained Reconfigurable Arrays (CGRAs) have emerged as promising candidates for such workloads due to their spatial architecture and run-time reconfigurability. However, ad-hoc hardware configurations and traditional static compilation techniques struggle to cope with the run-time irregularity and control-flow dynamism. This paper first presents a systematic design space exploration (DSE) to identify the optimized hardware configurations tailored to application-specific constraints, such as area budget, throughput requirement, and throughput efficiency. Then, it proposes a communication-aware dynamic scheduling approach built on a hardware/software co-design that combines preloading and scoreboard mechanisms to minimize reconfiguration overhead while maximizing interconnect bandwidth utilization. Evaluated on the optimized configurations and the respective spectrum sensing benchmarks, the proposed scheduling method achieves up to 1.6 × performance improvement over a baseline and 1.3 × over an adapted state-of-the-art (SOTA) dynamic scheduling strategy.