AIPR: An Automated Instruction-Level Patching and Rewriting Framework for Sustainable RISC-V Research

Computer systems research faces significant challenges in reproducibility because of toolchain fragmentation and the rapid evolution of the RISC-V ecosystem. Many research artifacts stay as `digital tombstones’ because they lack stable build environments and suffer from undocumented dependencies. This work presents the AIPR (Automated Instruction-level Patching and Rewriting) framework to address the gap between unstable hardware specifications and reproducible research. The methodology shifts the focus from complex source-level recompilation to direct executable-level modification. A three-stage pipeline automates instruction-level analysis, immediate reconstruction, and binary patching in ELF binaries. Experimental evaluations with the V-FRONT RISC-V processor include 2000 independent trials. These trials verify the functional robustness of the framework under complex architectural constraints. Furthermore, the AIPR framework achieves a 29.57× speedup in artifact generation compared to traditional GCC-based flows.