A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor

Compliance testing is mandatory when implementing the hardware architecture of a specific instruction set. The official compliance test suite with handwritten test cases for RISC-V can be helpful for this task. However, a high-quality test suite requires significant manual effort and cannot easily adapt to specific processor hardware architecture organization implementation aspects such as single-cycle, multi-cycle, or pipeline (with a different number of pipeline stages) configurations, or include an additional co-processor. This paper uses the PATARA framework, based on the REVERSI approach, to generate randomized, self-testing test cases for any RISC-V hardware implementation. The REVERSI method verifies the functionality within the same test program without requiring a golden reference model (e.g., simulator) and speeds up post-silicon validation times. With extensions to cover all possible hardware architecture implementation hazards and cache misses, a 6 pipeline-stages RV32IM hardware architecture implementation is verified functionally, reaching up to 100 % condition coverage with the REVERSI self-testing approach against 78.94% coverage achieved by the official handwritten compliance test framework. Moreover, the self-testing framework is extended in this paper to verify a vertical vector co-processor. Similar to the REVERSI method, two calculation paths for instruction are created to verify the execution. The constraint random generated vector instructions get validated by a software twin, executed on the RISC-V processor. The code coverage of the co-processor reaches up to 100 % condition coverage with self-verification on the system.