SDCViT: a transformer-powered hierarchical framework for semiconductor defect detection and classification

As semiconductor technology keeps advancing with increased integration density and process complexity, precise and efficient defect classification has become a prerequisite for semiconductor manufacturing yield and quality. Traditional deep learning methods and convolutional neural networks (CNNs) may face great difficulties in dealing with complicated defect cases and mixed defects that occur in modern semiconductor manufacturing environments. In this regard, this study introduces SDCViT (Semiconductor Defect Classification Vision Transformer); this hierarchical model uses a Vision Transformer (ViT) with powerful representation capability for semiconductor-defect classification tasks. SDCViT has a multi-level classification architecture with a hierarchical structure that can properly classify single types of semiconductor defects and mixed semiconductor defects with complex structures comprising more than one semiconductor-defect type. SDCViT fully exploits the self-attention properties of vision transformers to capture semiconductor-defect properties efficiently. Experimental evaluations were conducted using the challenging semiconductor-defect classification dataset MixedWM38. SDCViT outperforms existing state-of-the-art semiconductor-defect classification models, including CNN architectures and transfer learning architectures for semiconductor-defect classification tasks, achieving a test accuracy of 98.46%. As a means to validate semiconductor-defect classification generalization capability for SDCViT, external validation experiments were done using another challenging dataset WM-811 K. This validates SDCViT's efficiency for semiconductor-defect classification capability. This SDCViT model uses Grad-CAM for visual interpretations of feature importance and explanations of SDCViT model predictions towards better semantics. The SDCViT model architecture also uses ablations to understand better the components that lead to enhanced efficiency. This article further explores integration strategies that facilitate the seamless incorporation of SDCViT into state-of-the-art semiconductor manufacturing environments. By situating SDCViT within Industry 4.0-oriented production ecosystems characterized by stringent precision requirements, advanced defect classification methodologies, and emerging quality assurance paradigms, the framework is better equipped to support contemporary inspection tasks and evolving manufacturing specifications. Consequently, these integration pathways indicate that SDCViT has significant potential to enhance operational efficiency and meet the increasingly complex requirements of future semiconductor manufacturing processes.