Equalization and Interference Cancellation in High-Speed Electrical Interconnects: A Comprehensive Review

High-speed electrical wireline links, spanning Serializer/Deserializer backplanes and cables, chip-to-chip and die-to-die interfaces, wide-parallel single-ended (SE) buses, and simultaneous-bidirectional (SBD) buses, increasingly operate under severe insertion loss, long channel memory, and strong multi-lane interference. Equalization is therefore a central enabler for reliable symbol recovery in the presence of inter-symbol interference (ISI), echo, and near-/far-end crosstalk. This review synthesizes recent principles, architectures, and silicon-proven implementations of wireline equalizers with an emphasis on practical hardware constraints. It further organizes key research trajectories in high-speed wireline communications across three domains: (i) Time-domain equalization and detection for ISI-limited channels, spanning feed-forward equalizers, latency-relaxed decision-feedback equalization architectures that mitigate stringent feedback-loop constraints, and partial-response signaling combined with reduced-complexity maximum-likelihood sequence detection to enhance resilience against extended channel memory. (ii) Advanced modulation and frequency-domain processing, marking the transition from conventional 4-level pulse-amplitude modulation toward higher-order constellations and multicarrier techniques, notably discrete multitone and orthogonal frequency-division multiplexing, which necessitates modulation-aware frequency-domain equalization and adaptive bit- and power-loading algorithms. (iii) Crosstalk and echo mitigation for dense SE and SBD systems, including cancellation filtering in a multiple-input multiple-output framework and coding-aided interference suppression approaches. Across these domains, we present the fundamental trade-offs between equalization performance, algorithmic convergence, power-area efficiency, and latency.