An Iterative Low Area‐Time ECPM Accelerator Over NIST‐256 Curve on FPGA Platform

The NIST‐256 Modular Multiplication (MM) algorithm (including three operations: multiplication, NIST‐256 reduction, and final reduction) is an efficient method that can reduce the computation time of elliptic curve point multiplication (ECPM) over the NIST‐256 curve. In this paper, we focus on an iterative low area‐time ECPM accelerator over the NIST‐256 curve on FPGA: (1) an iterative area‐efficient 256‐bit multiplication with DSP‐optimization is proposed to reduce the hardware resources, (2) a two‐stage NIST‐256 reduction and a LUT‐based final reduction are presented to avoid data hazards of ECPM, and (3) a parallel ECPM hardware architecture and a conflict‐free memory scheme are proposed to accelerate the ECPM operation. The proposed ECPM accelerator is implemented on Virtex‐7 FPGA platform. The implementation results show that the performance of the proposed ECPM accelerator is 86.7% better than that of the previous state‐of‐art reference when calculating one ECPM operation over NIST‐256 curve, and the area*time (AT) value is 74.1% of them.