A Highly Cost-Effective Online Error Detection and Mitigation Scheme for CNN Hardware Accelerators Based on Approximate PE

Recent advancements in artificial intelligence have led to the widespread use of convolutional neural networks (CNNs) in various fields. To improve hardware performance, numerous hardware accelerator circuits have been developed. However, the extensive use of processing elements (PEs) in these accelerators raises potential reliability concerns. Traditional modular redundancy techniques, while effective in error mitigation, come with substantial hardware costs. In this study, we introduce a cost-effective scheme designed for efficient on-line error detection and mitigation in CNNs. This scheme is based on innovative designs of approximate PEs. Specifically, we propose two potential designs for these approximate PEs and evaluate their cost-effectiveness. These approximate PEs, used in conjunction with the original PEs, form an Approximate Dual PE Redundancy (ADPR) and Approximate Triple PR Redundancy (ATPR) structure, which is essential for verifying the quality of PE computations. Additionally, we propose a novel error mitigation technique derived from our ADPR and ATPR structure, significantly enhancing the error tolerance of PEs. Notably, our approximate PE designs require only 64% of the area compared to previous designs, while maintaining similar levels of approximation errors.