The Deception of Sight: Camouflaging Chips Information Against Optical Probing Attacks By Selective Increase of Local Density

In recent years, a novel non-invasive laser-assisted attack known as Optical Probing (OP) has been demonstrated to effectively probe the internal state of integrated circuits. This attack exploits the relative transparency of the silicon substrate to Near-InfraRed (NIR) light, enabling optical access through the backside of the chip. Consequently, OP poses a significant threat to information processed or stored on the chip and may facilitate Intellectual Property (IP) theft or reverse engineering. Existing mitigation techniques can be broadly classified into three categories: (1) fabrication-level modifications, (2) sensor-based countermeasures, and (3) circuit-level design techniques. Fabrication-based countermeasures are costly and often incompatible with standard industrial manufacturing processes, limiting their practicality for OP-resilient chip design. Sensor-based countermeasures may be circumvented by adaptive attackers, whereas circuit-level techniques typically require modifications to the layout of standard-cell libraries. Such modifications are time-consuming and can introduce considerable PPA overheads relative to conventional standard-cell designs. Therefore, this study investigates whether increasing the local layout density around a target logic cell can enhance resilience against OP attacks without requiring modifications beyond the layout level. In this context, local density refers to the fraction of a predefined region surrounding the target cell that is occupied by neighboring logic cells and associated layout structures. Our methodology employs standard logic cells to protect the chip’s sensitive information from an adversary equipped with OP capabilities. We found that increasing the local density of surrounding logic cells near a target logic cell enhances overall reflection, effectively masking the reflection from the target logic cell. This can significantly improve the concealment of the secure cell’s information from the OP attack since the reflections from the neighboring logic cells overlap with the target logic cells that need to be secured. Hence, an adversary cannot distinguish the exact location of the source of reflection. We demonstrate that this methodology can effectively countermeasure against OP attacks by conducting detailed experiments on the relationship between density and reflection, using NAND, INVERTER, NOR, and Flip-Flop cells. We exhaustively evaluated thousands of placement strategies with varying densities to show the efficacy of our technique against OP attacks. Moreover, we demonstrate the integration of our OP attack mitigation technique into the ASIC flow for designing an AES-128 core. We demonstrate that our technique in the worst-case comes with a 1% increase in power consumption, a 1% increase in area, and no change in the operating frequency compared to the unprotected AES-128 core against OP attack.