AceTherm: Accelerated Thermal Analysis of Chiplet Integration Using Non-Conformal FEM

As advanced process nodes continue to scale, heterogeneous integration technologies such as 2.5D/3D packaging, chiplets, and high-bandwidth memory have been widely adopted. However, these advances introduce substantially higher power densities, more complex interconnection structures, and increasingly diverse material systems. The resulting localized hotspots raise reliability concerns such as electromigration, thermomechanical stress, and structural warpage, making layout-driven thermal simulation with balanced accuracy and efficiency essential for rapid design iterations. This paper proposes AceTherm, an automated thermal simulation framework driven by Graphic Data System (GDS) layout and Process Design Kit (PDK) process parameters, which integrates non-conformal finite element method with customized sparse-matrix solvers. By exploiting the layered structure of the chip architecture, the simulation domain is sampled and discretized with a non-conformal mesh and high-resolution material mapping, significantly reducing degrees of freedom (DOFs) while preserving accuracy. The mesh division and sampling resolution provide a two-level control for trading off accuracy and speed, and the convergence and error behavior are analyzed to characterize the discrete scheme of AceTherm. Exploiting the structural properties of the resulting coefficient matrix, AceTherm employs supernodal sparse Cholesky factorization to accelerate the solution process. Notably, the symbolic factorization can be reused across multiple thermal load scenarios when the mesh pattern remains unchanged. Numerical experiments show that the proposed method achieves a 104.6 × speedup over the conventional COMSOL solution and reaches up to 539.2 × in repeated or preset-parameter simulations, while maintaining the average temperature error below 1 K. The combination of high computational speed, layer-aware modeling, and sub-Kelvin accuracy positions AceTherm as a practical tool for thermal analysis and optimization in heterogeneous IC back-end design.