low-density parity-check (LDPC) codes are extensively utilized in triple-level cell (TLC) NAND flash memory due to their robust data error correction capability, with their performance dependent on the decoder’s iterative computation of the Log-Likelihood Ratio (LLR) messages transmitted by the NAND flash memory channel. However, implementing LDPC decoding algorithms in hardware necessitates the quantization of LLR messages due to limited hardware resources, which inevitably diminishes LLR accuracy and subsequently affects LDPC decoding performance. To mitigate this issue, we propose a classification-based graded LLR Quantization Scheme for 3D TLC NAND Flash, termed CGLLR. By employing the k-means clustering algorithm to categorize the quantized initial LLR messages from the channel, we apply distinct quantization factors to different categories of LLR values while preserving the relative magnitudes among the original LLR. This CGLLR strategy significantly enhances the resolution of LLR messages, thereby improving decoding performance. Experimental results demonstrate that the proposed CGLLR scheme reduces the average number of decoding iterations by 26.3% compared to the standard algorithm.
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Cui et al. (2026) studied this question.
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